Advances in semiconductor technology are now providing computer systems with ever increasing amounts of semiconductor memory storage. Such additional memory must be easily controllable and accessable on a timely basis so as not to impact the performance of the computer system.
Circuitry utilized to control the memory and generate memory timing signals has traditionally been centralized to minimize the amount of circuitry or hardware required. A centralized approach to providing memory timing, however, is accompanied by the problems of timing signal skew and signal delays, as the timing signals travel from the centralized controller to the various memory boards, and from memory board to memory board.
In addition to memory timing considerations, access to increasing amounts of semiconductor memory presents the additional problem of being able to decode a larger number of memory address lines necessary to address the increasing amounts of memory storage within a sufficiently short period of time so as not to seriously degrade system performance.